Non-volatile memory (NVM) technology has faced challenges in attempting to improve the writing/reading speed and injection efficiency of hot carriers into the tunneling oxide of a memory cell. Non-volatile memory (NVM) devices that utilize a channel hot electron (CHE) injection process are inefficient. This inefficiency results in a low writing speed and a need for a large area to adequately perform a hot electron injection process. Non-volatile memory (NVM) devices that utilize a Fowler-Nordheim tunneling process are efficient. However, the Fowler-Nordheim tunneling process has a low read performance.
This means that there is a fundamental limit on the speed and scaling of conventional non-volatile memory (NVM) devices.
FIG. 1 illustrates a schematic diagram of a prior art memory cell 100 of an electrically erasable programmable read only memory (EEPROM) device. Memory cell 100 includes one P-channel metal oxide semiconductor (PMOS) transistor 110 and one P-channel metal oxide semiconductor (PMOS) capacitor 120. The PMOS capacitor 120 is formed by connecting together the source, drain and substrate of a PMOS transistor.
The PMOS transistor 110 may be referred to as PMOS program transistor 110, while the PMOS capacitor 120 may be referred to as PMOS control capacitor 120. The gate of the PMOS program transistor 110 and the gate of the PMOS control capacitor 120 are connected together (i.e., shorted together) and are isolated from the other active elements. The shorted gates of the PMOS program transistor 110 and the PMOS control capacitor 120 are collectively referred to as a “floating gate” 130. Charges (in amounts that represent either a zero (“0”) representation or a one (“1”) representation) may be written to the floating gate 130. In order to avoid well bias interference, the PMOS program transistor 110 and the PMOS control capacitor 120 are each located in a separate N well.
The prior art memory cell 100 is written to by injecting drain avalanche hot electrons into the floating gate 130. For PMOS operation (as shown in FIG. 1) a low voltage is applied to the control gate and drain of PMOS control capacitor 120 and a high voltage is applied to the source/well of PMOS program transistor 110. The channel of PMOS program transistor 110 is turned on and hot electrons are generated at the high electric field region at the drain junction (designated “VINJ” in FIG. 1). With positive voltage on the control gate of PMOS control transistor 120, some hot electrons with high energy will pass through the silicon-silicon dioxide (Si—SiO2) potential barrier and be injected into the floating gate 130.
The prior art memory cell 100 is erased by applying a high voltage to the control gate of the PMOS control transistor 120 and to the ground drain and source of the PMOS program transistor 110. Electrons on the floating gate 130 will pass through the gate oxide between the floating gate 130 and the control gate of the PMOS control capacitor 120 by Fowler-Nordheim (FN) tunneling process and into the substrate. A description of the physics of the Fowler-Nordheim (FN) tunneling process is set forth in U.S. Pat. No. 5,225,362, which is incorporated herein by reference.
FIG. 2 illustrates a prior art structure 200 that illustrates the use of a plurality of silicon nanocrystals 210 on the surface of a tunnel oxide 220 grown on a silicon substrate. The silicon nanocrystals 210 function as the “floating gate.” The tunnel oxide 220 and the silicon nanocrystals 210 are covered with a gate oxide 230. A control gate 240 is located above the gate oxide 230.
During the erase process, electrons will pass from the silicon nanocrystals 210 through the gate oxide 230 to the control gate 240 by the Fowler-Nordheim (FN) tunneling process. The silicon nanocrystals 210 facilitate the passage of the electrons through the gate oxide 230.
Prior art silicon nanocrystals 210 are typically either spherical or hemispherical. A typical hemispherical silicon nanocrystal geometry is shown in FIG. 2. The hemispherical silicon nanocrystal geometry exposes the largest cross-section to the tunnel oxide 220 and provides the most efficient charge injection from the substrate (not shown). The erase process is less efficient likely because the electric field is uniformly distributed on the top surface of the silicon nanocrystals 210.
Accordingly, there is a need in the art for an improved non-volatile memory (NVM) device (and method of manufacture) that increases the erase efficiency while at the same time maintaining the advantages that are provided by the hemispherical silicon nanocrystals.